Since the invention of the integrated circuit (IC), semiconductor chip features have become exponentially smaller and the number of transistors per device exponentially larger. Advanced IC's with hundreds of millions of transistors at feature sizes of 0.25 micron, 0.18 micron, 0.10 micron, and less are becoming routine. Improvement in overlay tolerances in optical photolithography, and the introduction of new light sources with progressively shorter wavelengths, have allowed optical steppers to significantly reduce the resolution limit for semiconductor fabrication far beyond one micron. To continue to make chip features smaller, and increase the transistor density of semiconductor devices, IC's have begun to be manufactured that have features smaller than the lithographic wavelength.
Sub-wavelength lithography, however, places large burdens on optical lithographic processes. Resolution of anything smaller than a wavelength is generally quite difficult. Pattern fidelity can deteriorate dramatically in sub-wavelength lithography. Critical dimensions (CD's), which are the geometries and spacings used to monitor the pattern size and ensure that it is within the customer's specification, are especially important to have size maintenance during processing. Semiconductor features may deviate significantly in size and shape from the ideal pattern drawn by the circuit designer.
Among various resolution-enhancement technologies (RET's) that have been developed in recent decades, attenuated phase shift masks (APSM) have provided improved image contrast and lithographic resolution over standard binary masks. An attenuated PSM forms shift patterns through adjacent areas of quartz and a low-transmission material such as molybdenum silicide (MoSi). Unlike chrome, MoSi allows a small percentage of the light to pass through, such as 4%, 6%, 18%, and so on. The thickness of the MoSi is usually chosen so the light that does pass through is 180 degrees out of phase with the light that passes through the neighboring clear quartz areas. The APSM is usually fabricated with a double exposure process, because a border pattern as well as a shift pattern must be defined. This lengthens processing time, and thus increases semiconductor foundry costs. The border pattern is defined through an opaque material, such as chrome.
The conventional double exposure APSM fabrication process is shown in FIGS. 1A-1K. In FIG. 1A, the APSM 100 includes a transparent substrate 102, such as quartz. Over the transparent substrate 102 is an attenuated layer 104, such as MoSiO, and an opaque layer 106, such as chrome. Photoresist 108 is deposited over the opaque layer 106. In FIG. 1B, the first exposure takes place, by electron beam (e-beam) writing desired areas 110 within the photoresist 108. In FIG. 1C, the exposed areas 110 are developed, removing the photoresist 108 from the areas 110. In FIG. 1D, the opaque layer 106 is etched through the exposed areas 110, and in FIG. 1E, the photoresist 108 is removed, such as by photoresist stripping and subsequent cleaning of the APSM 100. Finally, in FIG. 1F, the attenuated layer 104 is etched through the exposed areas 110. Thus, the first exposure of the APSM fabrication process is for defining the shift pattern of the APSM 100 within the attenuated layer 104.
Next, in FIG. 1G, another layer of photoresist 112 is coated onto the APSM 100. In FIG. 1H, the second exposure takes place, via laser beam writing a desired area 114 within the photoresist 112. The second exposure process can take upwards of two-and-a-half hours, lengthening processing time of the APSM 100. The second exposure process is needed to define a border pattern for the APSM 100. In FIG. 1I, the exposed area 114 is developed, removing the photoresist 112 from the area 114. In FIG. 1J, the opaque layer 106 is etched through the exposed area 114. Finally, in FIG. 1K, the photoresist 112 is removed, such as by photoresist stripping and subsequent cleaning of the APSM 100. Thus, the second exposure of the double exposure APSM fabrication process is for defining the border pattern of the APSM 100 within the opaque layer 106, where the opaque layer 106 may be chrome.
As has been indicated, the second exposure of the APSM fabrication process can take upwards of two-and-a-half hours to be completed when using laser beam writing. This is disadvantageous, because it lengthens processing times for fabrication of APSM's, and thus increases semiconductor foundry cost and reduces throughput and efficiency. Therefore, there is a need for an improved double exposure APSM fabrication process. Such an improved process should not utilize laser beam writing for the second exposure of the double exposure process. For this and other reasons, there is a need for the present invention.